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Microprocessor

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A microprocessor is a <a href="Computer" title="Computer">computer</a> <a href="Processor_(computing)" title="Processor (computing)">processor</a> for which the data processing logic and control is included on a single <a href="Integrated_circuit" title="Integrated circuit">integrated circuit</a> (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's <a href="Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU). The IC is capable of interpreting and executing program instructions and performing arithmetic operations.<a href="#cite_note-1">[1]</a> The microprocessor is a multipurpose, <a href="Clock_signal" title="Clock signal">clock</a>-driven, <a href="Processor_register" title="Processor register">register</a>-based, <a href="Digital_integrated_circuit" class="mw-redirect" title="Digital integrated circuit">digital integrated circuit</a> that accepts <a href="Binary_code" title="Binary code">binary</a> data as input, processes it according to <a href="Instruction_(computing)" class="mw-redirect" title="Instruction (computing)">instructions</a> stored in its <a href="Computer_memory" title="Computer memory">memory</a>, and provides results (also in binary form) as output. Microprocessors contain both <a href="Combinational_logic" title="Combinational logic">combinational logic</a> and <a href="Sequential_logic" title="Sequential logic">sequential digital logic</a>, and operate on numbers and symbols represented in the <a href="Binary_number" title="Binary number">binary number</a> system.

The integration of a whole CPU onto a single or a few integrated circuits using <a href="Very-Large-Scale_Integration" class="mw-redirect" title="Very-Large-Scale Integration">Very-Large-Scale Integration</a> (VLSI) greatly reduced the cost of processing power. Integrated circuit processors are produced in large numbers by highly automated <a href="Metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Metal–oxide–semiconductor">metal–oxide–semiconductor</a> (MOS) <a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabrication processes</a>, resulting in a relatively low <a href="Unit_price" title="Unit price">unit price</a>. Single-chip processors increase reliability because there are fewer electrical connections that can fail. As <a href="Processor_design" title="Processor design">microprocessor designs</a> improve, the cost of manufacturing a chip (with smaller components built on a semiconductor chip the same size) generally stays the same, according to <a href="Rock's_law" class="mw-redirect" title="Rock's law">Rock's law</a>.

Before microprocessors, small computers had been built using racks of <a href="Circuit_board" class="mw-redirect" title="Circuit board">circuit boards</a> with many <a href="Medium-scale_integration" class="mw-redirect" title="Medium-scale integration">medium-</a> and <a href="Small-scale_integration" class="mw-redirect" title="Small-scale integration">small-scale integrated circuits</a>. These were typically of the <a href="Transistor%E2%80%93transistor_logic" title="Transistor–transistor logic">TTL</a> type. Microprocessors combined this into one or a few <a href="Large-scale_integration" class="mw-redirect" title="Large-scale integration">large-scale</a> ICs. While there is disagreement over who deserves credit for the invention of the microprocessor, the first commercially available microprocessor was the <a href="Intel_4004" title="Intel 4004">Intel 4004</a>, designed by <a href="Federico_Faggin" title="Federico Faggin">Federico Faggin</a> and introduced in 1971.<a href="#cite_note-IEEE-2">[2]</a>

Continued increases in microprocessor capacity have since rendered other forms of computers almost completely obsolete (see <a href="History_of_computing_hardware" title="History of computing hardware">history of computing hardware</a>), with one or more microprocessors used in everything from the smallest <a href="Embedded_system" title="Embedded system">embedded systems</a> and <a href="Handheld_device" class="mw-redirect" title="Handheld device">handheld devices</a> to the largest <a href="Mainframe" class="mw-redirect" title="Mainframe">mainframes</a> and <a href="Supercomputer" title="Supercomputer">supercomputers</a>.

A microprocessor is distinct from a <a href="Microcontroller" title="Microcontroller">microcontroller</a> including a <a href="System_on_a_chip" title="System on a chip">system on a chip</a>.<a href="#cite_note-Warnes_2003_pp._443–477-3">[3]</a> A microprocessor is related but distinct from a <a href="Digital_signal_processor" title="Digital signal processor">digital signal processor</a>, a specialized microprocessor chip, with its architecture optimized for the operational needs of <a href="Digital_signal_processing" title="Digital signal processing">digital signal processing</a>.<a href="#cite_note-4">[4]</a>: 104–107 <a href="#cite_note-Liptak-5">[5]</a>

<div class="mw-heading mw-heading2"><h2 id="Structure">Structure</h2></div>

The complexity of an integrated circuit is bounded by physical limitations on the number of <a href="Transistors" class="mw-redirect" title="Transistors">transistors</a> that can be put onto one chip, the number of package terminations that can connect the processor to other parts of the system, the number of interconnections it is possible to make on the chip, and the heat that the chip can <a href="Thermal_management_(electronics)" title="Thermal management (electronics)">dissipate</a>. Advancing technology makes more complex and powerful chips feasible to manufacture.

A minimal hypothetical microprocessor might include only an <a href="Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> (ALU), and a <a href="Control_logic" title="Control logic">control logic</a> section. The ALU performs addition, subtraction, and operations such as AND or OR. Each operation of the ALU sets one or more <a href="Bit_field" title="Bit field">flags</a> in a <a href="Status_register" title="Status register">status register</a>, which indicate the results of the last operation (zero value, negative number, <a href="Integer_overflow" title="Integer overflow">overflow</a>, or others). The control logic retrieves instruction codes from memory and initiates the sequence of operations required for the ALU to carry out the instruction. A single <a href="Operation_code" class="mw-redirect" title="Operation code">operation code</a> might affect many individual data paths, registers, and other elements of the processor.

As integrated circuit technology advanced, it was feasible to manufacture more and more complex processors on a single chip. The size of data objects became larger; allowing more transistors on a chip allowed <a href="Word_(computer_architecture)" title="Word (computer architecture)">word</a> sizes to increase from <a href="4-bit_computing" title="4-bit computing">4-</a> and <a href="8-bit" class="mw-redirect" title="8-bit">8-bit</a> words up to today's <a href="64-bit" class="mw-redirect" title="64-bit">64-bit</a> words. Additional features were added to the processor architecture; more on-chip registers sped up programs, and complex instructions could be used to make more compact programs. <a href="Floating-point_arithmetic" title="Floating-point arithmetic">Floating-point arithmetic</a>, for example, was often not available on 8-bit microprocessors, but had to be carried out in <a href="Software" title="Software">software</a>. Integration of the <a href="Floating-point_unit" title="Floating-point unit">floating-point unit</a>, first as a separate integrated circuit and then as part of the same microprocessor chip, sped up floating-point calculations.

Occasionally, physical limitations of integrated circuits made such practices as a <a href="Bit_slice" class="mw-redirect" title="Bit slice">bit slice</a> approach necessary. Instead of processing all of a long word on one integrated circuit, multiple circuits <a href="Parallel_computing" title="Parallel computing">in parallel</a> processed subsets of each word. While this required extra logic to handle, for example, carry and overflow within each slice, the result was a system that could handle, for example, <a href="32-bit" class="mw-redirect" title="32-bit">32-bit</a> words using integrated circuits with a capacity for only four bits each.

The ability to put large numbers of transistors on one chip makes it feasible to integrate memory on the same die as the processor. This <a href="CPU_cache" title="CPU cache">CPU cache</a> has the advantage of faster access than off-chip memory and increases the processing speed of the system for many applications. Processor <a href="Clock_frequency" class="mw-redirect" title="Clock frequency">clock frequency</a> has increased more rapidly than external memory speed, so <a href="Cache_memory" class="mw-redirect" title="Cache memory">cache memory</a> is necessary if the processor is not to be delayed by slower external memory.

The design of some processors has become complicated enough to be difficult to fully <a href="Integrated_circuit_testing" class="mw-redirect" title="Integrated circuit testing">test</a>, and this has caused problems at large cloud providers.<a href="#cite_note-6">[6]</a>

<div class="mw-heading mw-heading3"><h3 id="Special-purpose_designs">Special-purpose designs</h3></div>

A microprocessor is a general purpose processing entity. Several specialized processing devices have followed:

<ul><li>A <a href="Digital_signal_processor" title="Digital signal processor">digital signal processor</a> (DSP) is specialized for <a href="Signal_processing" title="Signal processing">signal processing</a>.</li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing units</a> (GPUs) are processors designed primarily for <a href="Real-time_rendering" class="mw-redirect" title="Real-time rendering">real-time rendering</a> of images.</li>

<li>Other specialized units exist for <a href="Video_processing" title="Video processing">video processing</a> and <a href="Vision_processing_unit" title="Vision processing unit">machine vision</a>. (See: <a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a>.)</li>

<li><a href="Microcontroller" title="Microcontroller">Microcontrollers</a> in <a href="Embedded_system" title="Embedded system">embedded systems</a> and <a href="Peripheral_device" class="mw-redirect" title="Peripheral device">peripheral devices</a>.</li>

<li><a href="Systems_on_chip" class="mw-redirect" title="Systems on chip">Systems on chip</a> (SoCs) often integrate one or more microprocessor and microcontroller cores with other components such as <a href="Radio_modem" title="Radio modem">radio modems</a>, and are used in smartphones and tablet computers.</li></ul>

<div class="mw-heading mw-heading3"><h3 id="Speed_and_power_considerations">Speed and power considerations</h3></div>

Microprocessors can be selected for differing applications based on their word size, which is a measure of their complexity. Longer word sizes allow each <a href="Clock_cycle" class="mw-redirect" title="Clock cycle">clock cycle</a> of a processor to carry out more computation, but correspond to physically larger integrated circuit dies with higher standby and operating <a href="Power_consumption" class="mw-redirect" title="Power consumption">power consumption</a>.<a href="#cite_note-cmicrotek-7">[7]</a> 4-, 8- or 12-bit processors are widely integrated into microcontrollers operating embedded systems. Where a system is expected to handle larger volumes of data or require a more flexible <a href="User_interface" title="User interface">user interface</a>, 16-, 32- or 64-bit processors are used. An 8- or <a href="16-bit" class="mw-redirect" title="16-bit">16-bit</a> processor may be selected over a 32-bit processor for <a href="System_on_a_chip" title="System on a chip">system on a chip</a> or microcontroller applications that require extremely <a href="Low-power_electronics" title="Low-power electronics">low-power electronics</a>, or are part of a <a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">mixed-signal integrated circuit</a> with noise-sensitive on-chip <a href="Analog_electronics" class="mw-redirect" title="Analog electronics">analog electronics</a> such as high-resolution analog to digital converters, or both.

Some people say that running 32-bit arithmetic on an 8-bit chip could end up using more power, as the chip must execute software with multiple instructions.<a href="#cite_note-8">[8]</a>

However, others say that modern 8-bit chips are always more power-efficient than 32-bit chips when running equivalent software routines.<a href="#cite_note-freeman-9">[9]</a>

<div class="mw-heading mw-heading2"><h2 id="Embedded_applications">Embedded applications</h2></div>

Thousands of items that were traditionally not computer-related include microprocessors. These include household <a href="Home_appliance" title="Home appliance">appliances</a>, vehicles (and their accessories), tools and test instruments, toys, light switches/dimmers and <a href="Arc-fault_circuit_interrupter" title="Arc-fault circuit interrupter">electrical circuit breakers</a>, smoke alarms, battery packs, and hi-fi audio/visual components (from <a href="DVD_player" title="DVD player">DVD players</a> to <a href="Phonograph#Turntable_technology" title="Phonograph">phonograph turntables</a>). Such products as cellular telephones, <a href="DVD_video" class="mw-redirect" title="DVD video">DVD video</a> system and <a href="HDTV" class="mw-redirect" title="HDTV">HDTV</a> broadcast systems fundamentally require consumer devices with powerful, low-cost, microprocessors. Increasingly stringent pollution control standards effectively require automobile manufacturers to use microprocessor engine management systems to allow optimal control of emissions over the widely varying operating conditions of an automobile. Non-programmable controls would require bulky, or costly implementation to achieve the results possible with a microprocessor.

A microprocessor control program (<a href="Embedded_software" title="Embedded software">embedded software</a>) can be tailored to fit the needs of a product line, allowing upgrades in performance with minimal redesign of the product. Unique features can be implemented in product line's various models at negligible production cost.

Microprocessor control of a system can provide control strategies that would be impractical to implement using electromechanical controls or purpose-built electronic controls. For example, an internal combustion engine's control system can adjust ignition timing based on engine speed, load, temperature, and any observed tendency for knocking—allowing the engine to operate on a range of fuel grades.

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

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</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></div>

The advent of low-cost <a href="Computers" class="mw-redirect" title="Computers">computers</a> on <a href="Integrated_circuits" class="mw-redirect" title="Integrated circuits">integrated circuits</a> has transformed <a href="Modern_society" class="mw-redirect" title="Modern society">modern society</a>. General-purpose microprocessors in <a href="Personal_computer" title="Personal computer">personal computers</a> are used for computation, text editing, <a href="Multimedia" title="Multimedia">multimedia display</a>, and communication over the <a href="Internet" title="Internet">Internet</a>. Many more microprocessors are part of <a href="Embedded_system" title="Embedded system">embedded systems</a>, providing digital control over myriad objects from appliances to automobiles to <a href="Cellular_phone" class="mw-redirect" title="Cellular phone">cellular phones</a> and industrial <a href="Process_control" class="mw-redirect" title="Process control">process control</a>. Microprocessors perform binary operations based on <a href="Boolean_logic" class="mw-redirect" title="Boolean logic">Boolean logic</a>, named after <a href="George_Boole" title="George Boole">George Boole</a>. The ability to operate computer systems using Boolean Logic was first proven in a 1938 thesis by master's student <a href="Claude_Shannon" title="Claude Shannon">Claude Shannon</a>, who later went on to become a professor. Shannon is considered "The Father of Information Theory". In 1951 <a href="Microprogramming" class="mw-redirect" title="Microprogramming">Microprogramming</a> was invented by <a href="Maurice_Wilkes" title="Maurice Wilkes">Maurice Wilkes</a> at the <a href="University_of_Cambridge" title="University of Cambridge">University of Cambridge</a>, UK, from the realisation that the central processor could be controlled by a specialised program in a dedicated <a href="ROM" class="mw-redirect" title="ROM">ROM</a>.<a href="#cite_note-10">[10]</a> Wilkes is also credited with the idea of symbolic labels, macros and subroutine libraries.<a href="#cite_note-11">[11]</a>

Following the development of <a href="MOS_integrated_circuit" class="mw-redirect" title="MOS integrated circuit">MOS integrated circuit</a> chips in the early 1960s, MOS chips reached higher <a href="Transistor_density" class="mw-redirect" title="Transistor density">transistor density</a> and lower manufacturing costs than <a href="Bipolar_junction_transistor" title="Bipolar junction transistor">bipolar</a> <a href="Integrated_circuits" class="mw-redirect" title="Integrated circuits">integrated circuits</a> by 1964. MOS chips further increased in complexity at a rate predicted by <a href="Moore's_law" title="Moore's law">Moore's law</a>, leading to <a href="Large-scale_integration" class="mw-redirect" title="Large-scale integration">large-scale integration</a> (LSI) with hundreds of <a href="Transistors" class="mw-redirect" title="Transistors">transistors</a> on a single MOS chip by the late 1960s. The application of MOS LSI chips to <a href="Computing" title="Computing">computing</a> was the basis for the first microprocessors, as engineers began recognizing that a complete <a href="Computer_processor" class="mw-redirect" title="Computer processor">computer processor</a> could be contained on several MOS LSI chips.<a href="#cite_note-ieee-12">[12]</a> Designers in the late 1960s were striving to integrate the <a href="Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU) functions of a computer onto a handful of MOS LSI chips, called microprocessor unit (MPU) chipsets.

While there is disagreement over who invented the microprocessor,<a href="#cite_note-IEEE-2">[2]</a><a href="#cite_note-13">[13]</a> the first commercially available microprocessor was the <a href="Intel_4004" title="Intel 4004">Intel 4004</a>, released as a single MOS LSI chip in 1971.<a href="#cite_note-14">[14]</a> The single-chip microprocessor was made possible with the development of MOS <a href="Silicon-gate" class="mw-redirect" title="Silicon-gate">silicon-gate</a> technology (SGT).<a href="#cite_note-silicon-gate-15">[15]</a> The earliest MOS transistors had <a href="Aluminium" title="Aluminium">aluminium</a> <a href="Metal_gate" title="Metal gate">metal gates</a>, which Italian physicist <a href="Federico_Faggin" title="Federico Faggin">Federico Faggin</a> replaced with <a href="Silicon" title="Silicon">silicon</a> <a href="Self-aligned_gate" title="Self-aligned gate">self-aligned gates</a> to develop the first silicon-gate MOS chip at <a href="Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild Semiconductor</a> in 1968.<a href="#cite_note-silicon-gate-15">[15]</a> Faggin later joined <a href="Intel" title="Intel">Intel</a> and used his silicon-gate MOS technology to develop the 4004, along with <a href="Marcian_Hoff" title="Marcian Hoff">Marcian Hoff</a>, <a href="Stanley_Mazor" title="Stanley Mazor">Stanley Mazor</a> and <a href="Masatoshi_Shima" title="Masatoshi Shima">Masatoshi Shima</a> in 1971.<a href="#cite_note-16">[16]</a> The 4004 was designed for <a href="Busicom" title="Busicom">Busicom</a>, which had earlier proposed a multi-chip design in 1969, before Faggin's team at Intel changed it into a new single-chip design. The <a href="4-bit" class="mw-redirect" title="4-bit">4-bit</a> Intel 4004 was soon followed by the 8-bit <a href="Intel_8008" title="Intel 8008">Intel 8008</a> in 1972. The MP944 chipset used in the <a href="F-14_CADC" title="F-14 CADC">F-14 Central Air Data Computer</a> in 1970 has also been cited as an early microprocessor, but was not known to the public until declassified in 1998.

Other <a href="Embedded_system" title="Embedded system">embedded</a> uses of 4-bit and 8-bit microprocessors, such as <a href="Computer_terminal" title="Computer terminal">terminals</a>, <a href="Computer_printer" class="mw-redirect" title="Computer printer">printers</a>, various kinds of <a href="Automation" title="Automation">automation</a> etc., followed soon after. Affordable 8-bit microprocessors with <a href="16-bit" class="mw-redirect" title="16-bit">16-bit</a> addressing also led to the first general-purpose <a href="Microcomputer" title="Microcomputer">microcomputers</a> from the mid-1970s on.

The first use of the term "microprocessor" is attributed to <a href="Viatron" title="Viatron">Viatron Computer Systems</a><a href="#cite_note-17">[17]</a> describing the custom integrated circuit used in their System 21 small computer system announced in 1968.

Since the early 1970s, the increase in capacity of microprocessors has followed <a href="Moore's_law" title="Moore's law">Moore's law</a>; this originally suggested that the number of components that can be fitted onto a chip doubles every year. With present technology, it is actually every two years,<a href="#cite_note-18">[18]</a> and as a result Moore later changed the period to two years.<a href="#cite_note-19">[19]</a>

<div class="mw-heading mw-heading3"><h3 id="First_projects">First projects</h3></div>

These projects delivered a microprocessor at about the same time: <a href="Garrett_AiResearch" title="Garrett AiResearch">Garrett AiResearch</a>'s <a href="Central_Air_Data_Computer" class="mw-redirect" title="Central Air Data Computer">Central Air Data Computer</a> (CADC) (1970), <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a>' TMS 1802NC (September 1971) and <a href="Intel" title="Intel">Intel</a>'s <a href="4004" class="mw-redirect" title="4004">4004</a> (November 1971, based on an earlier 1969 <a href="Busicom" title="Busicom">Busicom</a> design). Arguably, <a href="Four-Phase_Systems_AL1" title="Four-Phase Systems AL1">Four-Phase Systems AL1</a> microprocessor was also delivered in 1969.

<div class="mw-heading mw-heading4"><h4 id="Four-Phase_Systems_AL1_(1969)">Four-Phase Systems AL1 (1969)</h4></div>

The <a href="Four-Phase_Systems_AL1" title="Four-Phase Systems AL1">Four-Phase Systems AL1</a> was an 8-bit <a href="Bit_slice" class="mw-redirect" title="Bit slice">bit slice</a> chip containing eight registers and an ALU.<a href="#cite_note-20">[20]</a> It was designed by <a href="Lee_Boysel" title="Lee Boysel">Lee Boysel</a> in 1969.<a href="#cite_note-21">[21]</a><a href="#cite_note-22">[22]</a><a href="#cite_note-23">[23]</a> At the time, it formed part of a nine-chip, 24-bit CPU with three AL1s. It was later called a microprocessor when, in response to 1990s litigation by <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a>, Boysel constructed a demonstration system where a single AL1 with a 1969 datestamp formed part of a courtroom demonstration computer system, together with RAM, ROM, and an input-output device.<a href="#cite_note-24">[24]</a> The AL1 wasn't sold individually, but was part of the System IV/70 announced in September 1970 and first delivered in February 1972.<a href="#cite_note-:0-25">[25]</a>

<div class="mw-heading mw-heading4"><h4 id="Garrett_AiResearch_CADC_(1970)">Garrett AiResearch CADC (1970)</h4></div>

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<div role="note" class="hatnote navigation-not-searchable">Further information: <a href="F-14_CADC" title="F-14 CADC">F-14 CADC</a></div>

In 1968, <a href="Garrett_AiResearch" title="Garrett AiResearch">Garrett AiResearch</a> (who employed designers <a href="Ray_Holt_(computer_scientist)" title="Ray Holt (computer scientist)">Ray Holt</a> and Steve Geller) was invited to produce a digital computer to compete with <a href="Electromechanical" class="mw-redirect" title="Electromechanical">electromechanical</a> systems then under development for the main flight control computer in the <a href="US_Navy" class="mw-redirect" title="US Navy">US Navy</a>'s new <a href="F-14_Tomcat" class="mw-redirect" title="F-14 Tomcat">F-14 Tomcat</a> fighter. The design was complete by 1970, and used a <a href="MOSFET" title="MOSFET">MOS</a>-based chipset as the core CPU. The design was significantly (approximately 20 times) smaller and much more reliable than the mechanical systems it competed against and was used in all of the early Tomcat models. This system contained "a 20-bit, <a href="Pipeline_(computing)" title="Pipeline (computing)">pipelined</a>, <a href="Parallel_computing" title="Parallel computing">parallel</a> <a href="Multiprocessor" class="mw-redirect" title="Multiprocessor">multi-microprocessor</a>". The Navy refused to allow publication of the design until 1997. Released in 1998, the documentation on the <a href="Central_Air_Data_Computer" class="mw-redirect" title="Central Air Data Computer">CADC</a>, and the <a href="MP944" class="mw-redirect" title="MP944">MP944</a> chipset, are well known. Ray Holt's autobiographical story of this design and development is presented in the book: The Accidental Engineer.<a href="#cite_note-26">[26]</a><a href="#cite_note-27">[27]</a>

Ray Holt graduated from <a href="California_State_Polytechnic_University%2C_Pomona" title="California State Polytechnic University, Pomona">California State Polytechnic University, Pomona</a> in 1968, and began his computer design career with the CADC.<a href="#cite_note-28">[28]</a> From its inception, it was shrouded in secrecy until 1998 when at Holt's request, the US Navy allowed the documents into the public domain. Holt has claimed that no one has compared this microprocessor with those that came later.<a href="#cite_note-29">[29]</a> According to Parab et al. (2007), <style data-mw-deduplicate="TemplateStyles:r1244412712">

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</style><blockquote class="templatequote">The scientific papers and literature published around 1971 reveal that the MP944 digital processor used for the F-14 Tomcat aircraft of the US Navy qualifies as the first microprocessor. Although interesting, it was not a single-chip processor, as was not the Intel 4004 – they both were more like a set of parallel building blocks you could use to make a general-purpose form. It contains a CPU, <a href="RAM" class="mw-redirect" title="RAM">RAM</a>, <a href="ROM" class="mw-redirect" title="ROM">ROM</a>, and two other support chips like the Intel 4004. It was made from the same <a href="PMOS_logic" title="PMOS logic">P-channel</a> technology, operated at <a href="Military_specifications" class="mw-redirect" title="Military specifications">military specifications</a> and had larger chips – an excellent computer engineering design by any standards. Its design indicates a major advance over Intel, and two year earlier. It actually worked and was flying in the F-14 when the Intel 4004 was announced. It indicates that today's industry theme of converging <a href="Digital_signal_processor" title="Digital signal processor">DSP</a>-<a href="Microcontroller" title="Microcontroller">microcontroller</a> architectures was started in 1971.<a href="#cite_note-30">[30]</a></blockquote> This convergence of DSP and microcontroller architectures is known as a <a href="Digital_signal_controller" title="Digital signal controller">digital signal controller</a>.<a href="#cite_note-31">[31]</a>

<div class="mw-heading mw-heading4"><h4 id="Gilbert_Hyatt_(1970)">Gilbert Hyatt (1970)</h4></div>

In 1990, American engineer Gilbert Hyatt was awarded U.S. Patent No. 4,942,516,<a href="#cite_note-32">[32]</a> which was based on a 16-bit serial computer he built at his <a href="Northridge%2C_California" class="mw-redirect" title="Northridge, California">Northridge, California</a>, home in 1969 from boards of bipolar chips after quitting his job at <a href="Teledyne" class="mw-redirect" title="Teledyne">Teledyne</a> in 1968;<a href="#cite_note-IEEE-2">[2]</a><a href="#cite_note-LAT-33">[33]</a> though the patent had been submitted in December 1970 and prior to <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a>' filings for the TMX 1795 and TMS 0100, Hyatt's invention was never manufactured.<a href="#cite_note-LAT-33">[33]</a><a href="#cite_note-34">[34]</a><a href="#cite_note-35">[35]</a> This nonetheless led to claims that Hyatt was the inventor of the microprocessor and the payment of substantial royalties through a <a href="Philips_N.V." class="mw-redirect" title="Philips N.V.">Philips N.V.</a> subsidiary,<a href="#cite_note-36">[36]</a> until Texas Instruments prevailed in a complex legal battle in 1996, when the U.S. Patent Office overturned key parts of the patent, while allowing Hyatt to keep it.<a href="#cite_note-IEEE-2">[2]</a><a href="#cite_note-37">[37]</a> Hyatt said in a 1990 Los Angeles Times article that his invention would have been created had his prospective investors backed him, and that the venture investors leaked details of his chip to the industry, though he did not elaborate with evidence to support this claim.<a href="#cite_note-LAT-33">[33]</a> In the same article, The Chip author <a href="T.R._Reid" class="mw-redirect" title="T.R. Reid">T.R. Reid</a> was quoted as saying that historians may ultimately place Hyatt as a co-inventor of the microprocessor, in the way that Intel's Noyce and TI's Kilby share credit for the invention of the chip in 1958: "Kilby got the idea first, but Noyce made it practical. The legal ruling finally favored Noyce, but they are considered co-inventors. The same could happen here."<a href="#cite_note-LAT-33">[33]</a> Hyatt would go on to fight a decades-long legal battle with the state of California over alleged unpaid taxes on his patent's windfall after 1990, which would culminate in a landmark Supreme Court case addressing states' <a href="Sovereign_immunity" title="Sovereign immunity">sovereign immunity</a> in <a href="Franchise_Tax_Board_of_California_v._Hyatt_(2019)" class="mw-redirect" title="Franchise Tax Board of California v. Hyatt (2019)">Franchise Tax Board of California v. Hyatt (2019)</a>.

<div class="mw-heading mw-heading4"><h4 id="Texas_Instruments_TMX_1795_(1970–1971)">Texas Instruments TMX 1795 (1970–1971)</h4></div>

Texas Instruments developed in 1970–1971 a one-chip CPU replacement for the <a href="Datapoint_2200" title="Datapoint 2200">Datapoint 2200</a> terminal, the TMX 1795 (later TMC 1795). Like Intel's later <a href="8008" class="mw-redirect" title="8008">8008</a>, it was rejected by customer Datapoint. According to Gary Boone, the TMX 1795 never reached production. Still it reached a prototype state at 1971 February 24.<a href="#cite_note-righto_com-38">[38]</a> Since it was built to the same specification, its instruction set was very similar to the Intel 8008.<a href="#cite_note-genie-39">[39]</a><a href="#cite_note-shirriff-40">[40]</a>

<div class="mw-heading mw-heading4"><h4 id="Texas_Instruments_TMS_1802NC_(1971)">Texas Instruments TMS 1802NC (1971)</h4></div>

The TMS1802NC, announced September 17, 1971, was the first microcontroller and at launch implemented a four-function calculator. The TMS1802NC, despite its designation, was not part of the <a href="TMS_1000" class="mw-redirect" title="TMS 1000">TMS 1000</a> series; it was later redesignated as part of the TMS 0100 series, which was used in the TI Datamath calculator. It was marketed as a calculator-on-a-chip and also "fully programmable", but this programming had to done during manufacturing. Its chip integrated a CPU with an 11-bit instruction word, 3520 bits (320 instructions) of ROM and 182 bits of RAM.<a href="#cite_note-genie-39">[39]</a><a href="#cite_note-41">[41]</a><a href="#cite_note-shirriff-40">[40]</a><a href="#cite_note-42">[42]</a>

<div class="mw-heading mw-heading4"><h4 id="Pico/General_Instrument_(1971)">Pico/General Instrument (1971)</h4></div>

In 1971, Pico Electronics<a href="#cite_note-43">[43]</a> and <a href="General_Instrument" title="General Instrument">General Instrument</a> (GI) introduced their first collaboration in ICs, a complete single-chip calculator IC for the Monroe/<a href="Litton_Industries" title="Litton Industries">Litton</a> Royal Digital III calculator. This chip could also arguably lay claim to be one of the first microprocessors or microcontrollers having <a href="ROM" class="mw-redirect" title="ROM">ROM</a>, <a href="RAM" class="mw-redirect" title="RAM">RAM</a> and a <a href="RISC" class="mw-redirect" title="RISC">RISC</a> instruction set on-chip. The layout for the four layers of the <a href="PMOS_logic" title="PMOS logic">PMOS</a> process was hand drawn at x500 scale on mylar film, a significant task at the time given the complexity of the chip.

Pico was a spinout by five GI design engineers whose vision was to create single-chip calculator ICs. They had significant previous design experience on multiple calculator chipsets with both GI and <a href="Elliott_Automation" class="mw-redirect" title="Elliott Automation">Marconi-Elliott</a>.<a href="#cite_note-44">[44]</a> The key team members had originally been tasked by <a href="Elliott_Automation" class="mw-redirect" title="Elliott Automation">Elliott Automation</a> to create an 8-bit computer in MOS and had helped establish a MOS Research Laboratory in <a href="Glenrothes" title="Glenrothes">Glenrothes</a>, Scotland in 1967.

Calculators were becoming the largest single market for semiconductors so Pico and GI went on to have significant success in this burgeoning market. GI continued to innovate in microprocessors and microcontrollers with products including the CP1600, IOB1680 and PIC1650.<a href="#cite_note-45">[45]</a> In 1987, the GI Microelectronics business was spun out into the <a href="Microchip_Technology" title="Microchip Technology">Microchip</a> <a href="PIC_microcontroller" class="mw-redirect" title="PIC microcontroller">PIC microcontroller</a> business.

<div class="mw-heading mw-heading4"><h4 id="Intel_4004_(1971)">Intel 4004 (1971)</h4></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Intel_4004" title="Intel 4004">Intel 4004</a></div>

The <a href="Intel_4004" title="Intel 4004">Intel 4004</a> is often (falsely) regarded as the first true microprocessor built on a single chip,<a href="#cite_note-46">[46]</a><a href="#cite_note-47">[47]</a> priced at US$60 (equivalent to $470 in 2024).<a href="#cite_note-48">[48]</a> The first known advertisement for the 4004 is dated November 15, 1971, and appeared in <a href="Electronic_News" title="Electronic News">Electronic News</a>.<a href="#cite_note-49">[49]</a> The microprocessor was designed by a team consisting of Italian engineer <a href="Federico_Faggin" title="Federico Faggin">Federico Faggin</a>, American engineers <a href="Marcian_Hoff" title="Marcian Hoff">Marcian Hoff</a> and <a href="Stanley_Mazor" title="Stanley Mazor">Stanley Mazor</a>, and Japanese engineer <a href="Masatoshi_Shima" title="Masatoshi Shima">Masatoshi Shima</a>.<a href="#cite_note-50">[50]</a>

The project that produced the 4004 originated in 1969, when <a href="Busicom" title="Busicom">Busicom</a>, a Japanese calculator manufacturer, asked Intel to build a chipset for high-performance <a href="Desktop_calculator" class="mw-redirect" title="Desktop calculator">desktop calculators</a>. Busicom's original design called for a programmable chip set consisting of seven different chips. Three of the chips were to make a special-purpose CPU with its program stored in ROM and its data stored in shift register read-write memory. <a href="Ted_Hoff" class="mw-redirect" title="Ted Hoff">Ted Hoff</a>, the Intel engineer assigned to evaluate the project, believed the Busicom design could be simplified by using dynamic RAM storage for data, rather than shift register memory, and a more traditional general-purpose CPU architecture. Hoff came up with a four-chip architectural proposal: a ROM chip for storing the programs, a dynamic RAM chip for storing data, a simple <a href="I/O" class="mw-redirect" title="I/O">I/O</a> device, and a 4-bit central processing unit (CPU). Although not a chip designer, he felt the CPU could be integrated into a single chip, but as he lacked the technical know-how the idea remained just a wish for the time being.

While the architecture and specifications of the MCS-4 came from the interaction of Hoff with <a href="Stanley_Mazor" title="Stanley Mazor">Stanley Mazor</a>, a software engineer reporting to him, and with Busicom engineer <a href="Masatoshi_Shima" title="Masatoshi Shima">Masatoshi Shima</a>, during 1969, Mazor and Hoff moved on to other projects. In April 1970, Intel hired Italian engineer <a href="Federico_Faggin" title="Federico Faggin">Federico Faggin</a> as project leader, a move that ultimately made the single-chip CPU final design a reality (Shima meanwhile designed the Busicom calculator firmware and assisted Faggin during the first six months of the implementation). Faggin, who originally developed the <a href="Silicon_gate" class="mw-redirect" title="Silicon gate">silicon gate</a> technology (SGT) in 1968 at <a href="Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild Semiconductor</a><a href="#cite_note-51">[51]</a> and designed the world's first commercial integrated circuit using SGT, the Fairchild 3708, had the correct background to lead the project into what would become the first commercial general purpose microprocessor. Since SGT was his very own invention, Faggin also used it to create his new methodology for <a href="Random_logic" title="Random logic">random logic</a> design that made it possible to implement a single-chip CPU with the proper speed, power dissipation and cost. The manager of Intel's MOS Design Department was <a href="Leslie_L._Vad%C3%A1sz" title="Leslie L. Vadász">Leslie L. Vadász</a> at the time of the MCS-4 development but Vadász's attention was completely focused on the mainstream business of semiconductor memories so he left the leadership and the management of the MCS-4 project to Faggin, who was ultimately responsible for leading the 4004 project to its realization. Production units of the 4004 were first delivered to Busicom in March 1971 and shipped to other customers in late 1971.

<div class="mw-heading mw-heading3"><h3 id="8-bit_designs">8-bit designs</h3></div>

The <a href="Intel_4004" title="Intel 4004">Intel 4004</a> was followed in 1972 by the <a href="Intel_8008" title="Intel 8008">Intel 8008</a>, intel's first <a href="8-bit" class="mw-redirect" title="8-bit">8-bit</a> microprocessor.<a href="#cite_note-52">[52]</a> The 8008 was not, however, an extension of the 4004 design, but instead the culmination of a separate design project at Intel, arising from a contract with <a href="Datapoint" title="Datapoint">Computer Terminals Corporation</a>, of San Antonio TX, for a chip for a terminal they were designing,<a href="#cite_note-mit-comp-history-53">[53]</a> the <a href="Datapoint_2200" title="Datapoint 2200">Datapoint 2200</a>—fundamental aspects of the design came not from Intel but from CTC. In 1968, CTC's Vic Poor and Harry Pyle developed the original design for the <a href="Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> and operation of the processor. In 1969, CTC contracted two companies, <a href="Intel" title="Intel">Intel</a> and <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a>, to make a single-chip implementation, known as the CTC 1201.<a href="#cite_note-forgotten-history-54">[54]</a> In late 1970 or early 1971, TI dropped out being unable to make a reliable part. In 1970, with Intel yet to deliver the part, CTC opted to use their own implementation in the Datapoint 2200, using traditional TTL logic instead (thus the first machine to run "8008 code" was not in fact a microprocessor at all and was delivered a year earlier). Intel's version of the 1201 microprocessor arrived in late 1971, but was too late, slow, and required a number of additional support chips. CTC had no interest in using it. CTC had originally contracted Intel for the chip, and would have owed them US$50,000 (equivalent to $388,209 in 2024) for their design work.<a href="#cite_note-forgotten-history-54">[54]</a> To avoid paying for a chip they did not want (and could not use), CTC released Intel from their contract and allowed them free use of the design.<a href="#cite_note-forgotten-history-54">[54]</a> Intel marketed it as the 8008 in April, 1972, as the world's first 8-bit microprocessor. It was the basis for the famous "<a href="Mark-8" title="Mark-8">Mark-8</a>" computer kit advertised in the magazine <a href="Radio-Electronics" title="Radio-Electronics">Radio-Electronics</a> in 1974. This processor had an 8-bit data bus and a 14-bit address bus.<a href="#cite_note-55">[55]</a>

The 8008 was the precursor to the successful <a href="Intel_8080" title="Intel 8080">Intel 8080</a> (1974), which offered improved performance over the 8008 and required fewer support chips. Federico Faggin conceived and designed it using high voltage N channel MOS. The <a href="Zilog_Z80" title="Zilog Z80">Zilog Z80</a> (1976) was also a Faggin design, using low voltage N channel with depletion load and derivative Intel 8-bit processors: all designed with the methodology Faggin created for the 4004. <a href="Motorola" title="Motorola">Motorola</a> released the competing <a href="Motorola_6800" title="Motorola 6800">6800</a> in August 1974, and the similar <a href="MOS_Technology_6502" title="MOS Technology 6502">MOS Technology 6502</a> was released in 1975 (both designed largely by the same people). The 6502 family rivaled the Z80 in popularity during the 1980s.

A low overall cost, little packaging, simple <a href="Computer_bus" class="mw-redirect" title="Computer bus">computer bus</a> requirements, and sometimes the integration of extra circuitry (e.g. the Z80's built-in <a href="Memory_refresh" title="Memory refresh">memory refresh</a> circuitry) allowed the <a href="Home_computer" title="Home computer">home computer</a> "revolution" to accelerate sharply in the early 1980s. This delivered such inexpensive machines as the Sinclair <a href="ZX81" title="ZX81">ZX81</a>, which sold for US$99 (equivalent to $342.41 in 2024). A variation of the 6502, the <a href="MOS_Technology_6510" title="MOS Technology 6510">MOS Technology 6510</a> was used in the <a href="Commodore_64" title="Commodore 64">Commodore 64</a> and yet another variant, the 8502, powered the <a href="Commodore_128" title="Commodore 128">Commodore 128</a>.

<a href="Western_Design_Center" title="Western Design Center">The Western Design Center, Inc</a> (WDC) introduced the CMOS <a href="WDC_65C02" title="WDC 65C02">WDC 65C02</a> in 1982 and licensed the design to several firms. It was used as the CPU in the <a href="Apple_IIe" title="Apple IIe">Apple IIe</a> and <a href="Apple_IIc" title="Apple IIc">IIc</a> personal computers as well as in medical implantable grade <a href="Pacemaker" title="Pacemaker">pacemakers</a> and <a href="Defibrillator" class="mw-redirect" title="Defibrillator">defibrillators</a>, automotive, industrial and consumer devices. WDC pioneered the licensing of microprocessor designs, later followed by <a href="Arm_Holdings" title="Arm Holdings">ARM</a> (32-bit) and other microprocessor <a href="Intellectual_property" title="Intellectual property">intellectual property</a> (IP) providers in the 1990s.

Motorola introduced the <a href="Motorola_6809" title="Motorola 6809">MC6809</a> in 1978. It was an ambitious and well thought-through 8-bit design that was <a href="Source_compatible" class="mw-redirect" title="Source compatible">source compatible</a> with the <a href="Motorola_6800" title="Motorola 6800">6800</a>, and implemented using purely <a href="Electrical_wiring" title="Electrical wiring">hard-wired</a> logic (subsequent 16-bit microprocessors typically used <a href="Microcode" title="Microcode">microcode</a> to some extent, as <a href="Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a> design requirements were becoming too complex for pure hard-wired logic).

Another early 8-bit microprocessor was the <a href="Signetics_2650" title="Signetics 2650">Signetics 2650</a>, which enjoyed a brief surge of interest due to its innovative and powerful <a href="Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a>.

A seminal microprocessor in the world of spaceflight was <a href="RCA" title="RCA">RCA</a>'s <a href="RCA_1802" title="RCA 1802">RCA 1802</a> (aka CDP1802, RCA COSMAC) (introduced in 1976), which was used on board the <a href="Galileo_(spacecraft)" title="Galileo (spacecraft)">Galileo</a> probe to Jupiter (launched 1989, arrived 1995). RCA COSMAC was the first to implement <a href="CMOS" title="CMOS">CMOS</a> technology. The CDP1802 was used because it could be run at very <a href="Low-power_electronics" title="Low-power electronics">low power</a>, and because a variant was available fabricated using a special production process, <a href="Silicon_on_sapphire" title="Silicon on sapphire">silicon on sapphire</a> (SOS), which provided much better protection against <a href="Cosmic_radiation" class="mw-redirect" title="Cosmic radiation">cosmic radiation</a> and <a href="Electrostatic_discharge" title="Electrostatic discharge">electrostatic discharge</a> than that of any other processor of the era. Thus, the SOS version of the 1802 was said to be the first <a href="Radiation-hardened" class="mw-redirect" title="Radiation-hardened">radiation-hardened</a> microprocessor.

The RCA 1802 had a <a href="Static_logic_(digital_logic)" class="mw-redirect" title="Static logic (digital logic)">static design</a>, meaning that the <a href="Clock_frequency" class="mw-redirect" title="Clock frequency">clock frequency</a> could be made arbitrarily low, or even stopped. This let the <a href="Galileo_(spacecraft)" title="Galileo (spacecraft)">Galileo spacecraft</a> use minimum electric power for long uneventful stretches of a voyage. Timers or sensors would awaken the processor in time for important tasks, such as navigation updates, attitude control, data acquisition, and radio communication. Current versions of the Western Design Center 65C02 and 65C816 also have <a href="Static_core" title="Static core">static cores</a>, and thus retain data even when the clock is completely halted.

<div class="mw-heading mw-heading3"><h3 id="12-bit_designs">12-bit designs</h3></div>

The <a href="Intersil_6100" title="Intersil 6100">Intersil 6100</a> family consisted of a <a href="12-bit" class="mw-redirect" title="12-bit">12-bit</a> microprocessor (the 6100) and a range of peripheral support and memory ICs. The microprocessor recognised the DEC <a href="PDP-8" title="PDP-8">PDP-8</a> <a href="Minicomputer" title="Minicomputer">minicomputer</a> instruction set. As such it was sometimes referred to as the CMOS-PDP8. Since it was also produced by Harris Corporation, it was also known as the Harris HM-6100. By virtue of its CMOS technology and associated benefits, the 6100 was being incorporated into some military designs until the early 1980s.

<div class="mw-heading mw-heading3"><h3 id="16-bit_designs">16-bit designs</h3></div>

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</style><table class="sidebar nomobile nowraplinks plainlist"><tbody><tr><td class="sidebar-pretitle">Part of a series on</td></tr><tr><th class="sidebar-title-with-pretitle"> modes for the <a href="X86" title="X86">x86</a> architecture</th></tr><tr><td class="sidebar-content" style="text-align: left">

<ul><li><a href="Real_mode" title="Real mode">Real mode</a> (<a href="Intel_8086" title="Intel 8086">Intel 8086</a>)</li>

<li><a href="Intel_8080" title="Intel 8080">8080</a> emulation mode (<a href="NEC_V20" title="NEC V20">NEC V20/V30</a> only)</li>

<li><a href="Protected_mode" title="Protected mode">Protected mode</a> (<a href="Intel_80286" title="Intel 80286">Intel 80286</a>)</li>

<li><a href="Unreal_mode" title="Unreal mode">Unreal mode</a> (<a href="Intel_80286" title="Intel 80286">Intel 80286</a>)</li>

<li><a href="Virtual_8086_mode" title="Virtual 8086 mode">Virtual 8086 mode</a> (<a href="Intel_80386" class="mw-redirect" title="Intel 80386">Intel 80386</a>)</li>

<li><a href="System_Management_Mode" title="System Management Mode">System Management Mode</a> (<a href="Intel_80386" class="mw-redirect" title="Intel 80386">Intel 386SL</a>)</li>

<li><a href="Long_mode" title="Long mode">Long mode</a> (<a href="AMD_Athlon_64" class="mw-redirect" title="AMD Athlon 64">AMD Athlon 64</a>)</li>

<li><a href="X86_virtualization" title="X86 virtualization">x86 virtualization</a> (<a href="Intel_Pentium_4" class="mw-redirect" title="Intel Pentium 4">Intel Pentium 4</a>, <a href="AMD_Athlon_64" class="mw-redirect" title="AMD Athlon 64">AMD Athlon 64</a>)</li>

</tr><tr><td class="sidebar-below" style="font-weight: normal; font-style: italic">

First supported platform shown in parentheses</td></tr><tr><td class="sidebar-navbar"><style data-mw-deduplicate="TemplateStyles:r1239400231">

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The first multi-chip <a href="16-bit" class="mw-redirect" title="16-bit">16-bit</a> microprocessor was the <a href="National_Semiconductor" title="National Semiconductor">National Semiconductor</a> <a href="IMP-16" title="IMP-16">IMP-16</a>, introduced in early 1973. An 8-bit version of the chipset was introduced in 1974 as the IMP-8.

Other early multi-chip 16-bit microprocessors include the <a href="MCP-1600" title="MCP-1600">MCP-1600</a> that <a href="Digital_Equipment_Corporation" title="Digital Equipment Corporation">Digital Equipment Corporation (DEC)</a> used in the <a href="LSI-11" class="mw-redirect" title="LSI-11">LSI-11</a> OEM board set and the packaged <a href="PDP-11" title="PDP-11">PDP-11/03</a> <a href="Minicomputer" title="Minicomputer">minicomputer</a>—and the <a href="Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild Semiconductor</a> MicroFlame 9440, both introduced in 1975–76. In late 1974, National introduced the first 16-bit single-chip microprocessor, the <a href="National_Semiconductor_PACE" title="National Semiconductor PACE">National Semiconductor PACE</a>,<a href="#cite_note-56">[56]</a> which was later followed by an <a href="NMOS_logic" title="NMOS logic">NMOS</a> version, the <a href="INS8900" class="mw-redirect" title="INS8900">INS8900</a>.

Next in list is the <a href="General_Instrument_CP1600" title="General Instrument CP1600">General Instrument CP1600</a>, released in February 1975,<a href="#cite_note-57">[57]</a> which was used mainly in the <a href="Intellivision" title="Intellivision">Intellivision</a> console.

Another early single-chip 16-bit microprocessor was TI's <a href="TMS_9900" class="mw-redirect" title="TMS 9900">TMS 9900</a>, which was also compatible with their <a href="TI-990" title="TI-990">TI-990</a> line of minicomputers. The 9900 was used in the TI 990/4 minicomputer, the <a href="TI-99/4A" title="TI-99/4A">TI-99/4A</a> home computer, and the TM990 line of OEM microcomputer boards. The chip was packaged in a large ceramic 64-pin <a href="Dual_in-line_package" title="Dual in-line package">DIP package</a>, while most 8-bit microprocessors such as the Intel 8080 used the more common, smaller, and less expensive plastic 40-pin DIP. A follow-on chip, the TMS 9980, was designed to compete with the Intel 8080, had the full TI 990 16-bit instruction set, used a plastic 40-pin package, moved data 8 bits at a time, but could only address 16 <a href="Kilobyte" title="Kilobyte">KB</a>. A third chip, the TMS 9995, was a new design. The family later expanded to include the 99105 and 99110.

The <a href="Western_Design_Center" title="Western Design Center">Western Design Center</a> (WDC) introduced the CMOS <a href="65816" class="mw-redirect" title="65816">65816</a> 16-bit upgrade of the WDC CMOS <a href="65C02" class="mw-redirect" title="65C02">65C02</a> in 1984. The 65816 16-bit microprocessor was the core of the <a href="Apple_IIGS" title="Apple IIGS">Apple IIGS</a> and later the <a href="Super_Nintendo_Entertainment_System" title="Super Nintendo Entertainment System">Super Nintendo Entertainment System</a>, making it one of the most popular 16-bit designs of all time.

Intel "upsized" their 8080 design into the 16-bit <a href="Intel_8086" title="Intel 8086">Intel 8086</a>, the first member of the <a href="X86" title="X86">x86</a> family, which powers most modern <a href="IBM_PC_compatible" title="IBM PC compatible">PC</a> type computers. <a href="Intel" title="Intel">Intel</a> introduced the 8086 as a cost-effective way of porting software from the 8080 lines, and succeeded in winning much business on that premise. The <a href="8088" class="mw-redirect" title="8088">8088</a>, a version of the 8086 that used an 8-bit external data bus, was the microprocessor in the first <a href="IBM_PC" class="mw-redirect" title="IBM PC">IBM PC</a>. Intel then released the <a href="80186" class="mw-redirect" title="80186">80186</a> and <a href="80188" class="mw-redirect" title="80188">80188</a>, the <a href="80286" class="mw-redirect" title="80286">80286</a> and, in 1985, the 32-bit <a href="80386" class="mw-redirect" title="80386">80386</a>, cementing their PC market dominance with the processor family's backwards compatibility. The 80186 and 80188 were essentially versions of the 8086 and 8088, enhanced with some onboard peripherals and a few new instructions. Although Intel's 80186 and 80188 were not used in IBM PC type designs, second source versions from NEC, the <a href="NEC_V20" title="NEC V20">V20</a> and V30 frequently were. The 8086 and successors had an innovative but limited method of <a href="Memory_segmentation" title="Memory segmentation">memory segmentation</a>, while the 80286 introduced a full-featured segmented <a href="Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU). The 80386 introduced a flat 32-bit memory model with paged memory management.

The 16-bit Intel x86 processors up to and including the 80386 do not include <a href="Floating-point_unit" title="Floating-point unit">floating-point units (FPUs)</a>. Intel introduced the <a href="8087" class="mw-redirect" title="8087">8087</a>, <a href="80187" class="mw-redirect" title="80187">80187</a>, <a href="80287" class="mw-redirect" title="80287">80287</a> and <a href="80387" class="mw-redirect" title="80387">80387</a> math coprocessors to add hardware floating-point and transcendental function capabilities to the 8086 through 80386 CPUs. The 8087 works with the 8086/8088 and 80186/80188,<a href="#cite_note-58">[58]</a> the 80187 works with the 80186 but not the 80188,<a href="#cite_note-59">[59]</a> the 80287 works with the 80286 and the 80387 works with the 80386. The combination of an x86 CPU and an x87 coprocessor forms a single multi-chip microprocessor; the two chips are programmed as a unit using a single integrated instruction set.<a href="#cite_note-60">[60]</a> The 8087 and 80187 coprocessors are connected in parallel with the data and address buses of their parent processor and directly execute instructions intended for them. The 80287 and 80387 coprocessors are interfaced to the CPU through I/O ports in the CPU's address space, this is transparent to the program, which does not need to know about or access these I/O ports directly; the program accesses the coprocessor and its registers through normal instruction opcodes.

<div class="mw-heading mw-heading3"><h3 id="32-bit_designs">32-bit designs</h3></div>

16-bit designs had only been on the market briefly when <a href="32-bit" class="mw-redirect" title="32-bit">32-bit</a> implementations started to appear.

The most significant of the 32-bit designs is the <a href="Motorola_MC68000" class="mw-redirect" title="Motorola MC68000">Motorola MC68000</a>, introduced in 1979. The 68k, as it was widely known, had 32-bit registers in its programming model but used 16-bit internal data paths, three 16-bit Arithmetic Logic Units, and a 16-bit external data bus (to reduce pin count), and externally supported only 24-bit addresses (internally it worked with full 32 bit addresses). In <a href="PC-based_IBM-compatible_mainframes" class="mw-redirect" title="PC-based IBM-compatible mainframes">PC-based IBM-compatible mainframes</a> the MC68000 internal microcode was modified to emulate the 32-bit System/370 IBM mainframe.<a href="#cite_note-61">[61]</a> Motorola generally described it as a 16-bit processor. The combination of high performance, large (16 <a href="Megabyte" title="Megabyte">megabytes</a> or 224 bytes) memory space and fairly low cost made it the most popular <a href="CPU_design" class="mw-redirect" title="CPU design">CPU design</a> of its class. The <a href="Apple_Lisa" title="Apple Lisa">Apple Lisa</a> and <a href="Macintosh_128K" title="Macintosh 128K">Macintosh</a> designs made use of the 68000, as did other designs in the mid-1980s, including the <a href="Atari_ST" title="Atari ST">Atari ST</a> and <a href="Amiga" title="Amiga">Amiga</a>.

The world's first single-chip fully 32-bit microprocessor, with 32-bit data paths, 32-bit buses, and 32-bit addresses, was the <a href="AT%26T_Corporation" title="AT&T Corporation">AT&T</a> <a href="Bell_Labs" title="Bell Labs">Bell Labs</a> <a href="Bellmac_32" title="Bellmac 32">BELLMAC-32A</a>, with first samples in 1980, and general production in 1982.<a href="#cite_note-62">[62]</a><a href="#cite_note-63">[63]</a> After the <a href="Bell_System_divestiture" class="mw-redirect" title="Bell System divestiture">divestiture of AT&T</a> in 1984, it was renamed the WE 32000 (WE for <a href="Western_Electric" title="Western Electric">Western Electric</a>), and had two follow-on generations, the WE 32100 and WE 32200. These microprocessors were used in the AT&T 3B5 and 3B15 minicomputers; in the 3B2, the world's first desktop super microcomputer; in the "Companion", the world's first 32-bit <a href="Laptop" title="Laptop">laptop</a> computer; and in "Alexander", the world's first book-sized super microcomputer, featuring ROM-pack memory cartridges similar to today's gaming consoles. All these systems ran the <a href="UNIX_System_V" title="UNIX System V">UNIX System V</a> operating system.

The first commercial, single chip, fully 32-bit microprocessor available on the market was the <a href="HP_FOCUS" title="HP FOCUS">HP FOCUS</a>.

Intel's first 32-bit microprocessor was the <a href="IAPX_432" class="mw-redirect" title="IAPX 432">iAPX 432</a>, which was introduced in 1981, but was not a commercial success. It had an advanced <a href="Capability-based_security" title="Capability-based security">capability-based</a> <a href="Object_(computer_science)" title="Object (computer science)">object-oriented</a> architecture, but poor performance compared to contemporary architectures such as Intel's own 80286 (introduced 1982), which was almost four times as fast on typical benchmark tests. However, the results for the iAPX432 was partly due to a rushed and therefore suboptimal <a href="Ada_(programming_language)" title="Ada (programming language)">Ada</a> <a href="Compiler" title="Compiler">compiler</a>.

Motorola's success with the 68000 led to the <a href="MC68010" class="mw-redirect" title="MC68010">MC68010</a>, which added <a href="Virtual_memory" title="Virtual memory">virtual memory</a> support. The <a href="MC68020" class="mw-redirect" title="MC68020">MC68020</a>, introduced in 1984 added full 32-bit data and address buses. The 68020 became hugely popular in the <a href="Unix" title="Unix">Unix</a> supermicrocomputer market, and many small companies (e.g., <a href="Altos_Computer_Systems" title="Altos Computer Systems">Altos</a>, <a href="UNOS_(operating_system)" title="UNOS (operating system)">Charles River Data Systems</a>, <a href="Cromemco" title="Cromemco">Cromemco</a>) produced desktop-size systems. The <a href="MC68030" class="mw-redirect" title="MC68030">MC68030</a> was introduced next, improving upon the previous design by integrating the MMU into the chip. The continued success led to the <a href="MC68040" class="mw-redirect" title="MC68040">MC68040</a>, which included an <a href="Floating-point_unit" title="Floating-point unit">FPU</a> for better math performance. The 68050 failed to achieve its performance goals and was not released, and the follow-up <a href="Motorola_68060" title="Motorola 68060">MC68060</a> was released into a market saturated by much faster RISC designs. The 68k family faded from use in the early 1990s.

Other large companies designed the 68020 and follow-ons into embedded equipment. At one point, there were more 68020s in embedded equipment than there were <a href="Intel" title="Intel">Intel</a> Pentiums in PCs.<a href="#cite_note-64">[64]</a> The <a href="ColdFire" class="mw-redirect" title="ColdFire">ColdFire</a> processor cores are derivatives of the 68020.

During this time (early to mid-1980s), <a href="National_Semiconductor" title="National Semiconductor">National Semiconductor</a> introduced a very similar 16-bit pinout, 32-bit internal microprocessor called the NS 16032 (later renamed 32016), the full 32-bit version named the <a href="NS320xx" class="mw-redirect" title="NS320xx">NS 32032</a>. Later, National Semiconductor produced the <a href="NS320xx" class="mw-redirect" title="NS320xx">NS 32132</a>, which allowed two CPUs to reside on the same memory bus with built in arbitration. The NS32016/32 outperformed the MC68000/10, but the NS32332—which arrived at approximately the same time as the MC68020—did not have enough performance. The third generation chip, the NS32532, was different. It had about double the performance of the MC68030, which was released around the same time. The appearance of RISC processors like the AM29000 and MC88000 (now both dead) influenced the architecture of the final core, the NS32764. Technically advanced—with a superscalar RISC core, 64-bit bus, and internally overclocked—it could still execute Series 32000 instructions through real-time translation.

When National Semiconductor decided to leave the Unix market, the chip was redesigned into the Swordfish Embedded processor with a set of on-chip peripherals. The chip turned out to be too expensive for the <a href="Laser_printer" class="mw-redirect" title="Laser printer">laser printer</a> market and was killed. The design team went to Intel and there designed the Pentium processor, which is very similar to the NS32764 core internally. The big success of the Series 32000 was in the laser printer market, where the NS32CG16 with microcoded BitBlt instructions had very good price/performance and was adopted by large companies like Canon. By the mid-1980s, <a href="Sequent_Computer_Systems" title="Sequent Computer Systems">Sequent</a> introduced the first SMP server-class computer using the NS 32032. This was one of the design's few wins, and it disappeared in the late 1980s. The <a href="MIPS_architecture" title="MIPS architecture">MIPS</a> <a href="R2000_(microprocessor)" class="mw-redirect" title="R2000 (microprocessor)">R2000</a> (1984) and <a href="R3000" title="R3000">R3000</a> (1989) were highly successful 32-bit RISC microprocessors. They were used in high-end workstations and servers by <a href="Silicon_Graphics" title="Silicon Graphics">SGI</a>, among others. Other designs included the <a href="Zilog_Z80000" title="Zilog Z80000">Zilog Z80000</a>, which arrived too late to market to stand a chance and disappeared quickly.

The <a href="ARM_architecture_family" title="ARM architecture family">ARM</a> first appeared in 1985.<a href="#cite_note-65">[65]</a> This is a <a href="RISC" class="mw-redirect" title="RISC">RISC</a> processor design, which has since come to dominate the 32-bit <a href="Embedded_systems" class="mw-redirect" title="Embedded systems">embedded systems</a> processor space due in large part to its power efficiency, its licensing model, and its wide selection of system development tools. Semiconductor manufacturers generally license cores and integrate them into their own <a href="System_on_a_chip" title="System on a chip">system on a chip</a> products; only a few such vendors such as Apple are licensed to modify the ARM cores or create their own. Most <a href="Cell_phones" class="mw-redirect" title="Cell phones">cell phones</a> include an ARM processor, as do a wide variety of other products. There are microcontroller-oriented ARM cores without virtual memory support, as well as <a href="Symmetric_multiprocessor" class="mw-redirect" title="Symmetric multiprocessor">symmetric multiprocessor</a> (SMP) applications processors with virtual memory.

From 1993 to 2003, the 32-bit <a href="X86" title="X86">x86</a> architectures became increasingly dominant in <a href="Desktop_computer" title="Desktop computer">desktop</a>, <a href="Laptop" title="Laptop">laptop</a>, and server markets, and these microprocessors became faster and more capable. Intel had licensed early versions of the architecture to other companies, but declined to license the Pentium, so <a href="AMD" title="AMD">AMD</a> and <a href="Cyrix" title="Cyrix">Cyrix</a> built later versions of the architecture based on their own designs. During this span, these processors increased in complexity (transistor count) and capability (instructions/second) by at least three orders of magnitude. Intel's Pentium line is probably the most famous and recognizable 32-bit processor model, at least with the public at broad.

<div class="mw-heading mw-heading3"><h3 id="64-bit_designs_in_personal_computers">64-bit designs in personal computers</h3></div>

While <a href="64-bit" class="mw-redirect" title="64-bit">64-bit</a> microprocessor designs have been in use in several markets since the early 1990s (including the <a href="Nintendo_64" title="Nintendo 64">Nintendo 64</a> <a href="Gaming_console" class="mw-redirect" title="Gaming console">gaming console</a> in 1996), the early 2000s saw the introduction of 64-bit microprocessors targeted at the PC market.

With AMD's introduction of a 64-bit architecture backwards-compatible with x86, <a href="X86-64" title="X86-64">x86-64</a> (also called AMD64), in September 2003, followed by Intel's near fully compatible 64-bit extensions (first called IA-32e or EM64T, later renamed Intel 64), the 64-bit desktop era began. Both versions can run 32-bit legacy applications without any performance penalty as well as new 64-bit software. With operating systems <a href="Windows_XP_x64" class="mw-redirect" title="Windows XP x64">Windows XP x64</a>, <a href="Windows_Vista" title="Windows Vista">Windows Vista</a> x64, <a href="Windows_7" title="Windows 7">Windows 7</a> x64, <a href="Linux" title="Linux">Linux</a>, <a href="BSD" class="mw-redirect" title="BSD">BSD</a>, and <a href="MacOS" title="MacOS">macOS</a> that run 64-bit natively, the software is also geared to fully utilize the capabilities of such processors. The move to 64 bits is more than just an increase in register size from the IA-32 as it also doubles the number of general-purpose registers.

The move to 64 bits by <a href="PowerPC" title="PowerPC">PowerPC</a> had been intended since the architecture's design in the early 90s and was not a major cause of incompatibility. Existing integer registers are extended as are all related data pathways, but, as was the case with IA-32, both floating-point and vector units had been operating at or above 64 bits for several years. Unlike what happened when IA-32 was extended to x86-64, no new general purpose registers were added in 64-bit PowerPC, so any performance gained when using the 64-bit mode for applications making no use of the larger address space is minimal.

In 2011, ARM introduced the new 64-bit ARM architecture.

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a></div>

In the mid-1980s to early 1990s, a crop of new high-performance reduced instruction set computer (<a href="RISC" class="mw-redirect" title="RISC">RISC</a>) microprocessors appeared, influenced by discrete RISC-like CPU designs such as the <a href="IBM_801" title="IBM 801">IBM 801</a> and others. RISC microprocessors were initially used in special-purpose machines and <a href="Unix" title="Unix">Unix</a> <a href="Workstation" title="Workstation">workstations</a>, but then gained wide acceptance in other roles.

The first commercial RISC microprocessor design was released in 1984, by <a href="MIPS_Computer_Systems" class="mw-redirect" title="MIPS Computer Systems">MIPS Computer Systems</a>, the 32-bit <a href="R2000_(microprocessor)" class="mw-redirect" title="R2000 (microprocessor)">R2000</a> (the R1000 was not released). In 1986, HP released its first system with a <a href="PA-RISC" title="PA-RISC">PA-RISC</a> CPU. In 1987, in the non-Unix <a href="Acorn_computers" class="mw-redirect" title="Acorn computers">Acorn computers</a>' 32-bit, then cache-less, <a href="ARM2" class="mw-redirect" title="ARM2">ARM2</a>-based <a href="Acorn_Archimedes" title="Acorn Archimedes">Acorn Archimedes</a> became the first commercial success using the <a href="ARM_architecture" class="mw-redirect" title="ARM architecture">ARM architecture</a>, then known as Acorn RISC Machine (ARM); first silicon <a href="ARM1" class="mw-redirect" title="ARM1">ARM1</a> in 1985. The R3000 made the design truly practical, and the <a href="R4000" title="R4000">R4000</a> introduced the world's first commercially available 64-bit RISC microprocessor. Competing projects would result in the IBM <a href="IBM_POWER_Instruction_Set_Architecture" class="mw-redirect" title="IBM POWER Instruction Set Architecture">POWER</a> and <a href="Sun_Microsystems" title="Sun Microsystems">Sun</a> <a href="SPARC" title="SPARC">SPARC</a> architectures. Soon every major vendor was releasing a RISC design, including the <a href="AT%26T_CRISP" class="mw-redirect" title="AT&T CRISP">AT&T CRISP</a>, <a href="AMD_29000" class="mw-redirect" title="AMD 29000">AMD 29000</a>, <a href="Intel_i860" title="Intel i860">Intel i860</a> and <a href="Intel_i960" title="Intel i960">Intel i960</a>, <a href="Motorola_88000" title="Motorola 88000">Motorola 88000</a>, <a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a>.

In the late 1990s, only two 64-bit RISC architectures were still produced in volume for non-embedded applications: <a href="SPARC" title="SPARC">SPARC</a> and <a href="Power_ISA" title="Power ISA">Power ISA</a>, but as ARM has become increasingly powerful, in the early 2010s, it became the third RISC architecture in the general computing segment.

<div class="mw-heading mw-heading3"><h3 id="SMP_and_multi-core_design">SMP and multi-core design</h3></div>

SMP <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a><a href="#cite_note-66">[66]</a> is a configuration of two, four, or more CPU's (in pairs) that are typically used in servers, certain workstations and in desktop personal computers, since the 1990s. A <a href="Multi-core_processor" title="Multi-core processor">multi-core processor</a> is a single CPU that contains more than one microprocessor core.

This popular two-socket motherboard from <a href="ABIT_BP6" title="ABIT BP6">Abit</a> was released in 1999 as the first SMP enabled PC motherboard, the <a href="Intel_Pentium_Pro" class="mw-redirect" title="Intel Pentium Pro">Intel Pentium Pro</a> was the first commercial CPU offered to system builders and enthusiasts. The Abit BP9 supports two Intel Celeron CPU's and when used with a SMP enabled operating system (Windows NT/2000/Linux) many applications obtain much higher performance than a single CPU. The early <a href="Celeron" title="Celeron">Celerons</a> are easily overclockable and hobbyists used these relatively inexpensive CPU's clocked as high as 533Mhz - far beyond Intel's specification. After discovering the capacity of these motherboards Intel removed access to the multiplier in later CPU's.

In 2001 IBM released the <a href="POWER4" title="POWER4">POWER4</a> CPU, it was a processor that was developed over five years of research, began in 1996 using a team of 250 researchers. The effort to accomplish the impossible was buttressed by development of and through—remote-collaboration and assigning younger engineers to work with more experienced engineers. The teams work achieved success with the new microprocessor, Power4. It is a two-in-one CPU that more than doubled performance at half the price of the competition, and a major advance in computing. The business magazine eWeek wrote: "The newly designed 1GHz Power4 represents a tremendous leap over its predecessor". An industry analyst, Brad Day of Giga Information Group said: "IBM is getting very aggressive, and this server is a game changer".

The Power4 won "Analysts’ Choice Award for Best Workstation/Server Processor of 2001", and it broke notable records, including winning a contest against the best players on the Jeopardy!<a href="#cite_note-67">[67]</a> U.S. television show.

Intel's <a href="Yonah_(microprocessor)" title="Yonah (microprocessor)">codename Yonah</a> CPU's launched on Jan 6, 2006, and were manufactured with two dies packaged on a <a href="Multi-chip_module" title="Multi-chip module">multi-chip module</a>. In a hotly contested marketplace <a href="List_of_AMD_processors" title="List of AMD processors">AMD</a> and others released new versions of multi-core CPU's, AMD's SMP enabled <a href="Athlon_MP" class="mw-redirect" title="Athlon MP">Athlon MP</a> CPU's from the <a href="Athlon-XP" class="mw-redirect" title="Athlon-XP">AthlonXP</a> line in 2001, Sun released the <a href="UltraSPARC_T1" title="UltraSPARC T1">Niagara</a> and <a href="Niagara_2" class="mw-redirect" title="Niagara 2">Niagara 2</a> with eight-cores, AMD's <a href="Athlon_64_X2" title="Athlon 64 X2">Athlon X2</a> was released in June 2007. The companies were engaged in a never-ending race for speed, indeed more demanding software mandated more processing power and faster CPU speeds.

By 2012 dual and quad-core processors became widely used in PCs and laptops, newer processors - similar to the higher cost professional level Intel Xeon's - with additional cores that execute instructions in parallel so software performance typically increases, provided the software is designed to utilize advanced hardware. Operating systems provided support for multiple-cores and SMD CPU's, many software applications including large workload and resource intensive applications - such as 3-D games - are programmed to take advantage of multiple core and multi-CPU systems.

Apple, Intel, and AMD currently lead the market with multiple core desktop and workstation CPU's. Although they frequently leapfrog each other for the lead in the performance tier. Intel retains higher frequencies and thus has the fastest single core performance,<a href="#cite_note-68">[68]</a> while AMD is often the leader in multi-threaded routines due to a more advanced ISA and the process node the CPU's are fabricated on.

<a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a> concepts for multi-core/multi-cpu configurations are related to <a href="Amdahl's_law" title="Amdahl's law">Amdahl's law</a>.

<div class="mw-heading mw-heading2"><h2 id="Market_statistics">Market statistics</h2></div>

In 1997, about 55% of all <a href="CPU" class="mw-redirect" title="CPU">CPUs</a> sold in the world were 8-bit <a href="Microcontroller" title="Microcontroller">microcontrollers</a>, of which over 2 billion were sold.<a href="#cite_note-69">[69]</a>

In 2002, less than 10% of all the CPUs sold in the world were 32-bit or more. Of all the 32-bit CPUs sold, about 2% are used in desktop or laptop personal computers. Most microprocessors are used in embedded control applications such as household appliances, automobiles, and computer peripherals. Taken as a whole, the average price for a microprocessor, microcontroller, or <a href="Digital_signal_processor" title="Digital signal processor">DSP</a> is just over US$6 (equivalent to $10.49 in 2024).<a href="#cite_note-turley-70">[70]</a>

In 2003, about $44 billion (equivalent to about $75 billion in 2024) worth of microprocessors were manufactured and sold.<a href="#cite_note-71">[71]</a> Although about half of that money was spent on CPUs used in desktop or laptop <a href="Personal_computer" title="Personal computer">personal computers</a>, those count for only about 2% of all CPUs sold.<a href="#cite_note-turley-70">[70]</a> The quality-adjusted price of laptop microprocessors improved −25% to −35% per year in 2004–2010, and the rate of improvement slowed to −15% to −25% per year in 2010–2013.<a href="#cite_note-Sun_2014-72">[72]</a>

About 10 billion CPUs were manufactured in 2008. Most new CPUs produced each year are embedded.<a href="#cite_note-73">[73]</a>

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<ul><li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison of instruction set architectures</a></li>

<li><a href="Computer_architecture" title="Computer architecture">Computer architecture</a></li>

<li><a href="Computer_engineering" title="Computer engineering">Computer engineering</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous computing</a></li>

<li><a href="List_of_microprocessors" title="List of microprocessors">List of microprocessors</a></li>

<li><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>

<li><a href="Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li></ul>

</div>

<div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2></div>

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"Basically, by getting your work done faster, you can put the CPU in sleep mode for longer periods of time. Thus, 32-bit MCUs are more power-efficient than 8-bit MCUs, right? Wrong."

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</style><a rel="nofollow" class="external text" href="https://patents.google.com/patent/US4942516A">US 4942516</a>, Hyatt, Gilbert P, "Single chip integrated circuit computer architecture", issued 17 July 1990<span class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.number=4942516&rft.cc=US&rft.title=Single+chip+integrated+circuit+computer+architecture&rft.inventor=Hyatt&rft.date=1990-07-17">  <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120525061939/http://www.google.com/patents/about?id=cNcbAAAAEBAJ">Archived</a> 25 May 2012 at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a>

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<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<ul><li><cite id="CITEREFRayBhurchand2013" class="citation book cs1">Ray, A. K.; Bhurchand, K.M. (2013). Advanced Microprocessors and Peripherals (3rd ed.). India: Tata McGraw-Hill. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-1-259-02977-6</bdi>. <a href="OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/878079623">878079623</a>.</cite></li></ul>

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<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

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<div class="side-box-text plainlist">Wikiversity has learning resources about <a href="https://en.wikiversity.org/wiki/Introduction_to_Computers/Processor" class="extiw external" title="v:Introduction to Computers/Processor">Introduction to Computers/Processor</a></div></div>

</div>

<div class="side-box-text plainlist">Wikimedia Commons has media related to <a href="https://commons.wikimedia.org/wiki/Category:Microprocessors" class="extiw external" title="commons:Category:Microprocessors">Microprocessors</a>.</div></div>

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<ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140502002437/http://wikipcpedia.com/pc-moments-33-the-microprocessor-1971/">Patent problems</a></li>

<li><cite id="CITEREFDirk_Oppelt" class="citation web cs1">Dirk Oppelt. <a rel="nofollow" class="external text" href="http://www.cpu-collection.de/">"The CPU Collection"</a>. Retrieved 23 December 2009.</cite></li>

<li><cite id="CITEREFGennadiy_Shvets" class="citation web cs1">Gennadiy Shvets. <a rel="nofollow" class="external text" href="http://www.cpu-world.com/">"CPU-World"</a>. Retrieved 23 December 2009.</cite></li>

<li><cite id="CITEREFJérôme_Cremet" class="citation web cs1">Jérôme Cremet. <a rel="nofollow" class="external text" href="http://gecko54000.free.fr/">"The Gecko's CPU Library"</a>. Retrieved 23 December 2009.</cite></li>

<li><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://computer.howstuffworks.com/microprocessor.htm">"How Microprocessors Work"</a>. April 2000. Retrieved 23 December 2009.</cite></li>

<li><cite id="CITEREFWilliam_Blair" class="citation web cs1">William Blair. <a rel="nofollow" class="external text" href="http://diephotos.blogspot.com/">"IC Die Photography"</a>. Retrieved 23 December 2009.</cite></li>

<li><cite id="CITEREFJohn_Bayko2003" class="citation web cs1">John Bayko (December 2003). <a rel="nofollow" class="external text" href="https://archive.today/20130415225040/http://www.takisnet.org/~jbayko/cpu/cpu.html">"Great Microprocessors of the Past and Present"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.takisnet.org/~jbayko/cpu/cpu.html">the original</a> on 15 April 2013. Retrieved 23 December 2009.</cite></li>

<li><cite id="CITEREFWade_Warner2004" class="citation web cs1">Wade Warner (22 December 2004). <a rel="nofollow" class="external text" href="https://www.ibm.com/developerworks/library/pa-microhist/">"Great moments in microprocessor history"</a>. IBM. Retrieved 7 March 2013.</cite></li>

<li><cite id="CITEREFArthur_Daemmrich_and_Sharon_Klotz2019" class="citation web cs1">Arthur Daemmrich and Sharon Klotz (12 December 2019). <a rel="nofollow" class="external text" href="https://www.si.edu/media/NMAH/NMAH-AC1504-Hyatt_Gil_Oral_History_transcript_FINAL.pdf">"Gilbert Hyatt"</a> (PDF). Smithsonian Institution.</cite></li></ul>

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</style></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies439" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Processor_technologies439" style="font-size:114%;margin:0 4em"><a href="Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Abstract_machine" title="Abstract machine">Abstract machine</a></li>

<li><a href="Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li>

<li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>

<li><a href="Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li>

<li><a href="Queue_automaton" title="Queue automaton">Queue automaton</a></li>

<li><a href="Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li>

<li><a href="Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li>

<li><a href="Turing_machine" title="Turing machine">Turing machine</a>

<ul><li><a href="Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li>

<li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal</a></li>

<li><a href="Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li>

<li><a href="Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li>

<li><a href="Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li>

<li><a href="Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li>

<li><a href="Hypercomputation" title="Hypercomputation">Hypercomputation</a></li>

<li><a href="Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li>

<li><a href="History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li>

<li><a href="Stack_machine" title="Stack machine">Stack machine</a></li>

<li><a href="Register_machine" title="Register machine">Register machines</a>

<ul><li><a href="Counter_machine" title="Counter machine">Counter</a></li>

<li><a href="Pointer_machine" title="Pointer machine">Pointer</a></li>

<li><a href="Random-access_machine" title="Random-access machine">Random-access</a></li>

<li><a href="Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>

<li><a href="Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li>

<li><a href="Harvard_architecture" title="Harvard architecture">Harvard</a>

<ul><li><a href="Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>

<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li>

<li><a href="Cellular_architecture" title="Cellular architecture">Cellular</a></li>

<li><a href="Endianness" title="Endianness">Endianness</a></li>

<li><a href="Computer_data_storage" title="Computer data storage">Memory access</a>

<li><a href="Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li>

<li><a href="Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li>

<li><a href="Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li>

<li><a href="Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a>

<ul><li><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></li>

<li><a href="Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li>

<li><a href="Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li>

<li><a href="Fabric_computing" title="Fabric computing">Fabric</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Cognitive_computing" title="Cognitive computing">Cognitive</a></li>

<li><a href="Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li>

<li><a href="Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li>

<ul><li><a href="TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Quantum_computing" title="Quantum computing">Quantum computing</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a>

<ul><li><a href="Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li>

<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li>

<li>Power

<ul><li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li>

<li><a href="PowerPC" title="PowerPC">PowerPC</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li></ul></li>

<li><a href="Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li>

<li><a href="SPARC" title="SPARC">SPARC</a></li>

<li><a href="SuperH" title="SuperH">SuperH</a></li>

<li><a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li>

<li><a href="ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li>

<li><a href="Unicore" title="Unicore">Unicore</a></li>

<li><a href="IA-64" title="IA-64">Itanium</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li>System/3x0

<li><a href="Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li>

<li>Tilera ISA</li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Adapteva" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>

<li><a href="Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li>

<li><a href="Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Data_dependency" title="Data dependency">Data dependency</a></li>

<li><a href="Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li>

<li><a href="Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li>

<li><a href="False_sharing" title="False sharing">False sharing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Scoreboarding" title="Scoreboarding">Scoreboarding</a></li>

<li><a href="Tomasulo's_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a>

<ul><li><a href="Reservation_station" title="Reservation station">Reservation station</a></li>

<li><a href="Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li>

<li><a href="Register_renaming" title="Register renaming">Register renaming</a></li>

<li><a href="Wide-issue" title="Wide-issue">Wide-issue</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Branch_predictor" title="Branch predictor">Branch prediction</a></li>

<li><a href="Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li>

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>

<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelining</a>

<ul><li><a href="Scalar_processor" title="Scalar processor">Scalar</a></li>

<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li>

<ul><li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>

<li><a href="Process_(computing)" title="Process (computing)">Process</a></li></ul></li>

<ul><li><a href="Vector_processor" title="Vector processor">Vector</a></li></ul></li>

<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>

<li><a href="Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>

<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a>

<ul><li><a href="Hyper-threading" title="Hyper-threading">Hyperthreading</a></li>

<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li>

<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a></li>

<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>

<li><a href="Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_performance" title="Computer performance">Processor performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor_count" title="Transistor count">Transistor count</a></li>

<li><a href="Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC)

<ul><li><a href="Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li>

<li><a href="Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li>

<li><a href="FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li>

<li><a href="Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li>

<li><a href="SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>

<li><a href="Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li>

<li><a href="Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li>

<li><a href="Vector_processor" title="Vector processor">Vector</a></li>

<li><a href="Barrel_processor" title="Barrel processor">Barrel</a></li>

<li><a href="Stream_processing" title="Stream processing">Stream</a></li>

<li><a href="Tile_processor" title="Tile processor">Tile processor</a></li>

<li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>

<li><a href="System_in_a_package" title="System in a package">System in a package</a> (SiP)</li>

<li><a href="Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Embedded_system" title="Embedded system">Embedded system</a></li>

<li><a href="Microcontroller" title="Microcontroller">Microcontroller</a></li>

<li><a href="Mobile_processor" title="Mobile processor">Mobile</a></li>

<li><a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li>

<li><a href="Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li>

<li><a href="Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li>

<li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_acceleration" title="Hardware acceleration">Hardware accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a></li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>

<li><a href="Image_processor" title="Image processor">Image processor</a></li>

<li><a href="Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li>

<li><a href="Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li>

<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li>

<li><a href="Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li>

<li><a href="Network_processor" title="Network processor">Network processor</a></li>

<li><a href="Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Bit_slicing" title="Bit slicing">bit slicing</a></li>

<li><a href="Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a>

<ul><li><a href="Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single-core" title="Single-core">Single-core</a></li>

<li><a href="Multi-core_processor" title="Multi-core processor">Multi-core</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Cache_(computing)" title="Cache (computing)">Cache</a>

<ul><li><a href="CPU_cache" title="CPU cache">CPU cache</a></li>

<li><a href="Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li>

<li><a href="Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li>

<li><a href="Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>

<li><a href="Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li>

<li><a href="Cache_coherence" title="Cache coherence">coherence</a></li></ul></li>

<li><a href="Clock_rate" title="Clock rate">Clock rate</a></li>

<li><a href="Clock_signal" title="Clock signal">Clock signal</a></li>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Execution_unit" title="Execution unit">Functional units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li>

<li><a href="Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li>

<li><a href="Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li>

<li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)

<ul><li><a href="Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li>

<li><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li>

<li><a href="Branch_predictor" title="Branch predictor">Branch predictor</a></li>

<li><a href="Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li>

<li><a href="Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC)

<ul><li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li>

<li><a href="Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Combinational_logic" title="Combinational logic">Combinational</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a>

<ul><li><a href="Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li>

<li><a href="Gate_array" title="Gate array">Array</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Processor_register" title="Processor register">Processor register</a></li>

<li><a href="Status_register" title="Status register">Status register</a></li>

<li><a href="Stack_register" title="Stack register">Stack register</a></li>

<li><a href="Register_file" title="Register file">Register file</a></li>

<li><a href="Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li>

<li><a href="Memory_address_register" title="Memory address register">Memory address register</a></li>

<li><a href="Program_counter" title="Program counter">Program counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li>

<li><a href="Instruction_unit" title="Instruction unit">Instruction unit</a></li>

<li><a href="Data_buffer" title="Data buffer">Data buffer</a></li>

<li><a href="Write_buffer" title="Write buffer">Write buffer</a></li>

<li><a href="Microcode" title="Microcode">Microcode</a> <a href="ROM_image" title="ROM image">ROM</a></li>

<li><a href="Counter_(digital)" title="Counter (digital)">Counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multiplexer" title="Multiplexer">Multiplexer</a></li>

<li><a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li>

<li><a href="Adder_(electronics)" title="Adder (electronics)">Adder</a></li>

<li><a href="Binary_multiplier" title="Binary multiplier">Multiplier</a>

<li><a href="Binary_decoder" title="Binary decoder">Binary decoder</a>

<ul><li><a href="Address_decoder" title="Address decoder">Address decoder</a></li>

<li><a href="Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li>

<li><a href="Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li>

<li><a href="Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean</a></li>

<li><a href="Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li>

<li><a href="Analogue_electronics" title="Analogue electronics">Analog</a></li>

<li><a href="Quantum_circuit" title="Quantum circuit">Quantum</a></li>

<li><a href="Switch#Electronic_switches" title="Switch">Switch</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Power_management" title="Power management">Power management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li>

<li><a href="Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li>

<li><a href="Clock_gating" title="Clock gating">Clock gating</a></li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li>

<li><a href="Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li>

<li><a href="Processor_design" title="Processor design">Processor design</a></li>

<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>

<li><a href="Hardware_security_module" title="Hardware security module">Hardware security module</a></li>

<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li>

<li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Pin_grid_array" title="Pin grid array">Pin grid array</a></li>

<li><a href="Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul>

</div></td></tr></tbody></table></div>

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</style></div><div role="navigation" class="navbox authority-control" aria-labelledby="Authority_control_databases_frameless&#124;text-top&#124;10px&#124;alt=Edit_this_at_Wikidata&#124;link=https&#58;//www.wikidata.org/wiki/Q5297#identifiers&#124;class=noprint&#124;Edit_this_at_Wikidata1357" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Authority_control_databases_frameless&#124;text-top&#124;10px&#124;alt=Edit_this_at_Wikidata&#124;link=https&#58;//www.wikidata.org/wiki/Q5297#identifiers&#124;class=noprint&#124;Edit_this_at_Wikidata1357" style="font-size:114%;margin:0 4em">Authority control databases </div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">International</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"><ul><li><a rel="nofollow" class="external text" href="https://id.worldcat.org/fast/1020008">FAST</a></li></ul></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">National</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"><ul><li><a rel="nofollow" class="external text" href="https://d-nb.info/gnd/4039232-6">Germany</a></li><li><a rel="nofollow" class="external text" href="https://id.loc.gov/authorities/sh85084898">United States</a></li><li><a rel="nofollow" class="external text" href="https://catalogue.bnf.fr/ark:/12148/cb119325021">France</a></li><li><a rel="nofollow" class="external text" href="https://data.bnf.fr/ark:/12148/cb119325021">BnF data</a></li><li><a rel="nofollow" class="external text" href="https://aleph.nkp.cz/F/?func=find-c&local_base=aut&ccl_term=ica=ph115311&CON_LNG=ENG">Czech Republic</a></li><li><a rel="nofollow" class="external text" href="https://datos.bne.es/resource/XX527982">Spain</a></li><li><a rel="nofollow" class="external text" href="https://www.nli.org.il/en/authorities/987007531452405171">Israel</a></li></ul></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"><ul><li><a rel="nofollow" class="external text" href="https://lux.collections.yale.edu/view/concept/e3215b94-3a62-4aaf-856f-58b8407af3cb">Yale LUX</a></li></ul></div></td></tr></tbody></table></div></div><div><div class="zim-footer">

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